1. Technical Field
The present invention relates generally to electrical circuits and in particular to use of transistor switches within electrical circuits. Still more particularly, the present invention relates to preventing latchup of transistor switches.
2. Description of the Related Art
Electrical switches are generally known in the art. FIG. 1A illustrates a conventional switch configuration, comprising a power supply 105 coupled via a switch 115 to a load 125. Power supply 105 and load 125 are in turn both connect to ground (GND) 120. A majority of electrical switches are implemented utilizing a transistor connected between the power source and the load. FIG. 2A illustrates one such switch configuration in which transistor 215 operates as the switch and is connected to output load impedance (referred to herein as ZL 225). Transistor 215 is switched on/off by applying/removing a gate voltage (gate 240) across the transistor's gate/source. During normal operation, when transistor 215 is turned on, transistor 215 exhibits certain operational characteristics that enable forward current flow from power supply 205 to ZL 225, generating a voltage across ZL 225. When transistor is turned off, however, no forward current flow passes through transistor 215 and thus, no current flow is expected through ZL 225.
One requirement for correct operation of P-channel transistors (and in particular those utilized in the above-described switch configuration) is that the transistor's body always be connected to the highest potential terminal of the two transistor terminals connecting the transistor to the circuit. Thus, as shown in FIG. 2A, transistor's body is connected (hard wired) to the power supply side terminal, which typically represents the terminal at the highest potential. The polarity of “VS1” indicates that the highest potential is at the side of the power supply terminal.
While the above configuration works in theory, since the transistor's body is biased to be always connected to the power supply side terminal, there are some implementations in which this configuration does not result in the transistor's body actually being connected to the highest potential terminal. For example, when transistor switches are utilized within inverter circuits, T-switches, and other such devices, the operation of the device occasionally results in higher potentials existing at the terminal not connected to the body of the transistor. Certain operational characteristics at the load end of the circuit device, such as reflections in transmission lines, for example, may result in a voltage across ZL that exceeds the potential seen at the power supply side terminal of the transistor. When this occurs, parasitic PN junctions within the transistor become forward biased and negatively affect the switching capability of the transistor and ultimately the device. This undesirable phenomenon is referred to as latch-up. A description of latch-up in transistor circuits/devices is provided in the background section of U.S. Pat. No. 6,878,595. Relevant portions of that description are incorporated herein by reference.
Thus, as mentioned above, latch-up may occur in the single switch configuration (described above). Additionally, one other type of circuit device in which latch-up is frequently encountered is the T-switch. During micro-circuit wafer or module testing, oftentimes switching between power domains is necessary. A conventional T-switch circuit design utilized for testing is illustrated within the circuit diagrams of FIG. 1B and 1C. As shown, two power supplies, primary supply 105 and secondary supply 110, are connected via switches 115/120 to load 125. Both power supplies provide power to a load 125, which is connected to one of the respective power supplies when a corresponding switch (switch1 115 for primary supply 105 and switch2 120 for secondary supply 110) is closed. Each leg of the circuit is connected to ground (GND) 130.
The two modes of operation of circuit 100 are illustrated. In normal mode, switch 1115 is closed, while switch2 120 is open, connecting load 125 to primary supply 105. During test mode, the state of the switches are reversed, i.e., switch2 120 is closed, while switch1 115 is open, whereby load 125 is connected to secondary supply 110.
FIG. 2B and 2C illustrates the transistor-enabled T-switch topology, which is well known in the art. With a conventional T-switch configured circuit, voltage across each switch may change polarity depending on the given switch state. As shown, the switches within a T-switch are two P-channel CMOS (complementary metal oxide semiconductor) transistors, switch1 transistor 215 and switch2 transistor 220, connected drain-to-drain in series with each other. A third transistor, N-channel transistor 235, connects at the drain-to-drain node of the two P-channel transistors. Each transistor receives a gate voltage input (Gate) 240, which turns switch1 and switch2 transistors 215, 220 off while N-channel transistor 235 is on, and vice versa. In this illustration, impedance ZL 225 represents the load being powered by either primary power supply 205 or secondary power supply 210 depending on whether the circuit is operating in normal or switched (test) mode.
With the above conventional circuit design, changing polarities across the T-switch may cause CMOS latchup exposure due to hard-wired body connections (shown connected to the positive voltage polarities (left and right, respectively) of switch1 transistor 215 and switch2 transistor 220. For normal operation, each P-channel transistor body should be tied toward the highest diffusion potentials, such that the voltage potential of the body of the transistor is not lower than that of the transistor's source or drain. This characteristic prevents forward biasing of the transistor's parasitic PN junction and the resulting latchup of the chip. For switched operation (when testing the wafer, for example), the P-channel body of switch2 transistor 120 becomes reversed-biased (change in voltage polarity) until the impedance (i.e., capacitance—C—within the load) is charged, risking potential latchup of the chip.
One proposed method of reducing the occurrence of latchup during the above described switching operations is by providing guard rings around the transistors. However, to substantially lower the risk for latchup, substantial guard-ringing is required, impacting the physical size (and cost) of the device (cell). Ultimately, the use of guard rings may not be sufficiently robust to prevent latchup.